Modern electronic devices are often made up of large numbers of sub-components such as latches and gates, embodied in transistors, which frequently number in the millions. In some cases, the functional design of an electrical or electronic device includes electrical paths that pass through a single latch to a large number of other sub-components (sometimes referred to as “output sinks”). This is especially true for devices in early stages of the development cycle, before optimization and refinement of the design. The greater the number of output sinks loading a latch, called the “fanout,” the higher the load on the latch and the higher the delay of the path from the latch through the output sinks.
Latch cloning, sometimes referred to as “latch replication”, has long been an effective tool to improve overall delay for paths with large fanouts. Broadly, latch cloning reduces the total output load of the sinks collectively by dividing the load between the original latch and one or more clones of the original latch. In some cases, latch cloning includes improving the latch position to a more optimal location in the circuit layout. There are two particularly well known methods for cloning a latch.
First is the traditional “manual” method, wherein the design engineer performs a manual process to identify which latches are suitable for cloning. Having selected a latch to clone, the design engineer manually allocates the output sinks of the selected latch among the clones and the original latch. One skilled in the art will appreciate that this approach reduces the fanout for the original latch by dividing the electrical load among multiple latches. Lastly, the design engineer modifies the hardware description language (HDL) representation of the design to include the cloned latches and the new output sink allocations.
There are three major disadvantages to the manual method. First, it is often very difficult for the designer to split certain components, such as a bus, for example, into discrete collections of output sinks. The challenges associated with splitting such components tends to produce resultant HDL representations that are very difficult to read, which makes the HDL representation difficult to understand and optimize.
Second, because the designer typically works with behavioral representations of the design, the designer rarely knows the specific layout positions of the latches or their output sinks. Thus, while the designer may produce a design that is optimal from a logic perspective, the designer cannot compare the physical performance of competing designs. As such, the designer may not be able to produce an optimal allocation of output sinks among the latch and its clones.
Third, the HDL representation of the entire design tends to change frequently, especially in the earlier stages of development. As such, even if the designer does overcome the first two challenges, the effort may be wasted when a design revision changes the HDL representation such that what was once an optimal overall solution is no longer optimal. In the manual method, the designer must manually update the HDL representation each time there is a change to that logic cone (that is, the downstream logic to which the output sinks connect) to achieve the best allocation. For these reasons, design engineers developed the second method for latch cloning.
The second traditional method for latch cloning involves serial loading the scan chains. Broadly, serially loading the scan chains occurs when the inbound scan chain loading signal on one latch is different from the inbound scan chain loading signal on a different latch of the same logic cone. The second traditional method overcomes some of the manual method's disadvantages in that synthesis tools can now optimally allocate the latch sinks during each synthesis run. Further, the second traditional method does not require the designer to split the output sinks manually.
But the second traditional method also suffers from drawbacks. For example, the second traditional method offers only limited visibility to the test team during debug and bring-up. The issue arises in that the test cases for each logic cone are different and therefore the inbound scan chain signals are different. This causes significant difficulty during fault diagnostics, which can cause challenges that outweigh the benefits of the second traditional method.
Other approaches have also been attempted, but also suffer from drawbacks. For example, for many circuit optimization techniques, there are tools configured to provide automatic implementation of the technique. But typical attempts to automate latch cloning have caused the standard verification tools and design-for-test (DFT) tools to fail.